1. The complement of the function F = (A + B’)(C’ + D)(B’ + C) is:

2. To put the 8085 microprocessor in the wait state

3. Comparing the time T1 taken for a single instruction on a pipelined CPU with time T2 taken on a non­ pipelined but identical CPU, we can say that

4. The 8085 microprocessor responds to the presence of an interrupt

5. The most appropriate matching for the following pairs X: Indirect addressing 1 : Loops Y: Immediate addressing 2 : Pointers Z: Auto decrement addressing 3: Constants is

6. Consider the values A = 2.0 x 10^30, B =-2.0 x 10^30, C= 1.0, and the sequence X: = A + B Y: = A + C X: = X + C Y: = Y + B executed on a computer where floating-point numbers are represented with 32 bits. The values for X and Y will be

7. A low memory can be connected to 8085 by using

8. Suppose a processor does not have any stack pointer register. Which of the following statements is true?

9. A processor needs software interrupt to

10. A CPU has two modes-privileged and non-privileged. In order to change the mode from privileged to non-privileged

11. Which is the most appropriate match for the items in the first column with the items in the second column: X. Indirect Addressing I. Array implementation Y. Indexed Addressing II. Writing re-locatable code Z. Base Register Addressing III. Passing array as parameter

12. The 2’s complement representation of (−539)10 in hexadecimal is

13. A device employing INTR line for device interrupt puts the CALL instruction on the data bus while

14. The 2' s complement representation of the decimal value - 15 is

15. Sign extension is a step in

16. In 2' s complement addition, overflow

17. In the absolute addressing mode

18. What are the states of the Auxiliary Carry (AC) and Carry Flag (dCY) after executing the following 8085 program? MVI L, 5DH MVI L, 6BH MOV A, H ADD L

19. The performance of a pipelined processor suffers if

20. Horizontal microprogramming :

21. Assuming all numbers are in 2's complement representation, which of the following numbers is divisible by 11111011?

22. For a pipelined CPU with a single ALU, consider the following situations 1. The j + 1-st instruction uses the result of the j-th instruction as an operand 2. The execution of a conditional jump instruction 3. The j-th and j + 1-st instructions require the ALU at the same time Which of the above can cause a hazard ?

23. Consider the grammar rule E → E1 - E2 for arith­metic expressions. The code generated is targeted to a CPU having a single user register. The sub­traction operation requires the first operand to be in the register. If E1 and E2 do not have any com­mon sub expression, in order to get the shortest possible code

24. If 73x (in base-x number system) is equal to 54y (in base-y number system), the possible values of x and y are

25. Which of the following addressing modes are suitable for program relocation at run time ?

26. Let A = 1111 1010 and B = 0000 1010 be two 8-bit 2's complement numbers. Their product in 2's complement is

27. A 4-stage pipeline has the stage delays as 150, 120, 160 and 140 nanoseconds respectively. Registers that are used between the stages have a delay of 5 nanoseconds each. Assuming constant clocking rate, the total time taken to process 1000 data items on this pipeline will be

28. Spatial locality refers to the problem that once a location is referenced

29. The Principle of locality justifies the use of

30. A system that has a lot of crashes, data should be written to the disk using?

31. Which addressing mode is suitable for a high-level language statement?

32. Which memory unit has the lowest access time?

33. In a 16-bit instruction code format 3-bit operation code, 12-bit address, and 1 bit is assigned for address mode designation. For indirect addressing, the mode bit is

34. A 32-bit address bus allows access to a memory of capability

35. Pipelining improves CPU performance due to?

36. The system bus consists of

37. An instruction cycle refers to

38. A hardware interrupt is

39. Which of the following is not involved in a memory write operation?

40. To prevent signals from colliding on the bus, ……………….. Prioritize access to memory by I/o channels and processors.

41. ………… improve system performance by temporarily storing data during transfers s/w devices or processers that operate at different speeds.

42. Addressing mode is …………………

43. Which of the following is not a valid class of interrupts? 1) Program 2) Timer 3) I/o 4) Hardware failure

44. System calls are usually invoked by using 1) An indirect jump 2) A software interrupt 3) Polling 4) A privileged instruction

45. Which of the following holds data and processing instructions temporarily until the CPU needs it??

46. Which of the following register processors used for fetch and execute operations? 1) Program counter 2) Instruction register 3) Address register

47. Microinstruction length is determined by ……………….. 1) The maximum number of simultaneous micro-operations that must be specified 2) The way in which the control information is represented or encoded 3) The way in which the next microinstruction address is specified

48. ID catching system, the memory reference made in any short time integral tends to use only a small fraction of the total memory?

49. The word length of a CPU is defined as

50. The register which holds the address of the locating to or from which data are to be transferred is known as